logic destroyer
@splinedrive
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A small step for a hobby logic designer, but a giant leap for
@tinytapeout
. The first official RISC-V uLinux ASIC, yes, ASIC, you heard that right, is operational and functional. Just dabbling in chip design as a hobbyist. Haha, what an awesome achievement! Thanx to
@matthewvenn
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Don't fuck with Linux systems engineers. The KianV RISC-V Linux SoC, running the latest stable Linux kernel 6.9.4, was published today :)
@obr2021
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Don't fuck with Linux systems engineers. The KianV RISC-V Linux SoC, running the latest stable Linux kernel 6.9.5, was published today :)
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Don't fuck with Linux systems engineers. The KianV RISC-V Linux SoC, running the latest stable Linux kernel 6.9.6, was published today :)
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Don't fuck with Linux systems engineers. The KianV RISC-V Linux SoC, running the latest stable Linux kernel 6.9.8, was published today :)
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Here is my first CPU, which I developed with trial and error without much knowledge. And then I decided to take an edX course in computer architecture by Harris, to transform my empirical knowledge into formal knowledge. And had started a reimplementation.
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With the knowledge I've now acquired, I absolutely must read Tanenbaum's book on operating system design again after this project, because now I will truly understand it. I've experienced everything myself, from virtual memory and networking to the exceptions that occur and their
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It's crazy that the KianV RV32IMA SV32 FPGA SoC has executed ~557 000 000 000 RISC-V instructions in 15 days, providing me with a fully functional Linux SoC. It’s unbelievable!
I’ve done many silly things, but the SoC just keeps working and working.
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In this thread, I will try to teach you about a RISC-V processor, piece by piece! You can take a look at the image that depicts the instructions and registers of an RV32I (simpelst) and ask questions before we gradually delve into the design.
#riscv
#twitterSchool
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Interested in a Linux RISC-V MMU system with the latest kernel 6.6.8 and easy to understand, as it's not rocket science? Yes, if so, then here's the Verilog source code. Have fun exploring.
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The Journey of an Embedded Systems Engineer: From Logic Design to Implementing a Linux SoC and Beyond
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So folks, let me introduce the KianV RISC-V SV32 RV32IMA Real MMU Linux SoC. I've hacked a bootloader that boots from an SD card, and the design worked without any problems right away. I'm both surprised and shocked, it took less than a month, and we can boot LINUX on the FPGA.
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Don't fuck with Linux systems engineers. The KianV RISC-V Linux SoC, running the latest stable Linux kernel 6.10.3, was published today :)
@obr2021
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I had originally planned not to write any Verilog for a few months. But I just got overwhelmed; it’s been raining outside the whole time. So, I'll just do a little bit, maybe for an hour at most. But it feels amazing!
🧡🥰 RISC-V
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Allow me to briefly introduce, this is my first CPU, which I obtained through the knowledge from the edX course, Building RISC-V. At the time, I didn't know that this is called a single cycle. I intuitively built a multi-cycle CPU because the memory must synchronously hold both
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I agree with that meme, it's going in the wrong direction. People are unable to write something from scratch. I don't know how such people can be productive. You should think in transistors and assembly instructions—that's the way 😂
No one understand the pain of Full Stack Developers 🤣🤣🤣
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Oh - wow! Simulation was right. First time right, time to market. See the improvement of my new simple
#dma
implementation to relieve
#kianRiscV
#riscv
#cpu
applications can use dma memcpy, memset: left
#ulx3s
dma based, right cpu based operations..I will share it next on github
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My first ASIC that I developed has arrived. I am overwhelmed. I am looking forward to testing my first design and others' as well. Long live
@tinytapeout
.
#TinyTapeOut
❤️🫵
@tnt
@UriShaked
@matthewvenn
@PsychogenicTech
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Reading this book and checking out my github implementation that follows it will give you understanding.
#riscv
#verilog
#coding
#understanding
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Oh, what madness! Now I have multiple UARTs, booting from the SD card, and even a C compiler, with which I can execute programs on my uLinux SoC that have been edited with vi. Oh man, I'm about to faint. RISC-V RV32IMA KianV SoC.
#tcc
#linux
#riscv
💯😂💢🙏
@samsoniuk
💢🙏
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Thank you,
@ATaylorFPGA
, for gifting me that amazing
#FPGA
#XILINX
#ARTIX
-7 wukong board from
#QMTech
@zyjnumber1
.
This board has both DDR and SDRAM on the PCB, which is really nice for porting Kianv RISC-V Linux SoC, with SDRAM as the first step.
Also, thanks to
@obr2021
,
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Now I have a real Linux machine accessible over the wide internet. GPIO, SD card, rv32ima sv32 Linux SoC, generic terminals, Ethernet says hello. The future belongs to KIANV RISC-V Linux machine, big thanks to
@ATaylorFPGA
and
@samsoniuk
, you know why :)
#fpga
#verilog
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I was criminally good today and initially introduced a TLB64. I've achieved a significant performance gain. The boot time has almost halved, the human shader is now 20 seconds faster. Telnet is also more responsive now. ❤️ to
@samsoniuk
KianV
#riscv
#Linux
@risc_v
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I love my
#LA5016
Logic Analyzer, I love being an engineer. Measure what your eye cannot see.
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Yes, that's how I learned to implement RISC-V.
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RISC-V Linux in a Nutshell
KianV RISC-V Linux SoC for teaching purposes.
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6.5 trillion instructions executed.
Before I started cleaning up the flat, I initiated a ping -A -s 50000 127.0.0.1 on my KianV FPGA Linux SoC. After I finished cleaning, I realized the RX and TX were over 1 GiB, meaning 2 GiB. My RISC-V machine was busy copying and processing in
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My journey with logic design began four years ago when I started reading Designing Video Game Hardware in Verilog by Steven Hugg
@8bitworkshop
. Since then, I haven't revisited it. Today, I'm picking it up again to see how it feels to read it now.
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In order to truly understand RISC-V, you need to first read these two basic specifications. It can be difficult at first, but as you gain more understanding, it starts to feel really rewarding.
The bible of the RISC-V CPU architect.
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Okay - over the summer, I asked
@Machdyne
to develop an ICE40HX8K with 32MB SDRAM. Here is the result. It's the first ICE40HX8K with SDRAM and uLinux in the world. This is a premiere, showing what can be achieved with ICE40s. Kuchen kianvV rv32ima uLinux SoC the future of joy.
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It's just awesome that I understand this right away now. Two years ago, I really struggled with it. I knew what it did as a black box, but I didn't understand the internal structure. But now, it's so obvious :)
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This book is the biggest shit of any book that has ever come across my desk. I had ordered the book on Amazon for 35 euros and was excited. Zero content and you can't read anything, the biggest nonsense ever.
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ARM is no longer up-to-date. ARM once caught up with MIPS, but now RISC-V will overtake it in the long run. I know it.
Why? Because everyone can create their own SoC, and through that, people can identify with and love RISC-V. When people use commercial cores, they understand
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As I say so nicely and always:
Don't fuck with Linux systems engineers. The KianV RISC-V Linux SoC, running the latest stable Linux kernel 6.9.9, was published today :)
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Hello from the KianV RISC-V Linux SoC. This machine is paying tribute to Ken Thompson and Dennis Ritchie, the founders and creators of UNIX and C. Enjoy.
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So far, it has been worthwhile to implement all of this. The book 'Computer Architecture' by a German pioneer Giloi reads very easily. I understand every sentence, what he means. Actually, one should read these books only after having experienced and developed everything oneself
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I motivated my 9-year-old son to develop an 8-bit binary counter as an ASIC using Wokwi, following certain instructions. Here is the result.
@WokwiMakes
@tinytapeout
@UriShaked
@matthewvenn
#wokwi
#asic
#dff
#binary
#counter
#revolution
#logicDestroyer
generation change, game
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What the hell, my first version of KianV RISC-V RV32IMA with a few extensions regarding control registers is going to silicon. Damn,
#TinyTapeOut
5.Thanks to all of you
@matthewvenn
,
@UriShaked
,
@tnt4all
,
@MoonbaseOtago
and everyone I haven't mentioned. TinyTapeOut rules.
@risc_v
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Allow me to introduce my
#RISCV
RV32 emulator that boots Linux without MMU, and where I know exactly what the kernel is doing!
#KianVEmulator
enjoy the video💯💥💢❤️💯💯❤️💯❤️💢❤️
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Don't fuck with Linux systems engineers. The KianV RISC-V Linux SoC, running the latest stable Linux kernel 6.9.7, was published today :)
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To be honest, when I see higher-level HDL languages like those based on Scala, I lose my motivation. It's so weird to me how people can ruin HDL. SystemVerilog has everything you need. I can't read Scala-based HDL; it just makes me feel strange.
Because hardware is just
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I'm glad that ETH Zurich is focusing on Verilog. Mostly in Europe/Germany, VHDL is represented, which I find crazy.
Here's a good introduction to Verilog. Very nice.
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Do you want an
#FPGA
running Linux, specifically
#Linux
implemented in
#Verilog
, for $20? It's user-friendly with the intention of being used for training purposes. Nothing complicated, all from one source. If so, give Kian's RISC-V a chance. Check
#riscv
New Linux kernel and cool new logo. It's fun. Moreover, QSPI is also working now. You don't need an SD card.
#kianRiscV
#riscv
@risc_v
#linux
for micros
#TangNano20k
@GOWIN_SEMI
@sipeed
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Do you remember my first RISC-V RV32IM CPU in Verilog from July 2021? If yes, it's "Straight Outta Compton" with a multiplier and divider, all nicely organized in one file. Kianv Origin.
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How cool is ModelSim. Really cool. Although I'm not really the wave diagram type, it's still somehow cool. I'm a bit baffled now, how silly GTKWave looks in comparison. Anyone interested in a free version of ModelSim under Linux, here's the link below. And then start doing
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Exactly 881 days ago, I ordered this open-source ASIC, and it arrived today. I thought it was crazy back then, but in the meantime, I have developed my own chip KianV uLinux SoC that can boot uLinux - ta-da! ;)
@efabless
CLEAR - The Open Source FPGA ASIC - by chipIgnite
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It's just fun to watch, when the device on your desk does whatever you want it to do and is nicely busy with its operating system. KianV RISC-V Linux SoC for teaching purposes.
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Don't fuck with Linux systems engineers. The KianV RISC-V SoC, running the latest mainline Linux kernel 6.11.0-rc7—now that's amazing ;)
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It's so crazy, I ordered Cynthion aka Luna 1088 days ago, half a lifetime. And today, after 1088 days, it arrived via FedEx. Back then, I was really in blinky logic design mode and had started my journey with my first CPU. Damn it!
@crowd_supply
@GSGlabs
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Allow me to introduce my latest product from
#logicDestroyer
. A RISC-V RV32E called KianV RV32E Baremetal Edition, which consumes relatively few resources. It's equipped with an audio device, as you know from my videos, a generic SPI controller for OLED and other fun, a UART, and
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RISC-V was the best move to create millions of logic designers by giving them access to CPU technology.
Because I'm reading Design of the RISC-V Instruction Set Architecture, I quote the following:
"ARMv7 is vast and complicated. Between ARM and Thumb, there are over 600 instructions in the integer ISA alone. NEON, the integer SIMD and floating-point extension, adds hundreds more.
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I had another design on TT05! An 8-Bit Shift Register with Output Latches 74HC595. I coded a C bit-banging code on my KianV RV32IMA SV32 system to create a Knight Rider effect. That means both the TTL chip and the Linux bit-banging system are my own designs from scratch. Thanx to
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Do you want to get started with RISC-V quickly, without using an FPGA or a logic simulator? Then get my RV32I RISC-V emulator, run 1.19 MicroPython on it, and analyze the emulator to understand RISC-V. Download it here
@risc_v
#rv32i
#riscv
#micropython
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That was an awesome project, an HDMI framebuffer with a RISC-V processor, still bare metal, had no idea about Linux SoC. Just a year ago. Crazy.
Of course, everything was implemented from scratch.
check my repo for it!
I haven't worked on my new
#riscv
cpu but i had much fun with my
#CmodA7
@DigilentInc
#fpga
board and ported my
#kianRiscV
#hdmi
soc on that powerful
#xilinx
board. Also I extend
#openfpgaloader
with cmoda7_35t support
@GwenhaelG
. Pull openfpgaloader and kianRiscV for cmoda7
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I'm digging into my old stuff. At the end of December 2020, I implemented HDMI and VGA stuff in Verilog. Here's the result.
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Ok, let's run the Linux kernel mainline 6.11.0 on the KianV RISC-V SoC and show the stamp of Ken Thompson, the guru.
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I'm thrilled that my project is being implemented on an FPGA. I have a passion for FPGAs and I dislike writing software, as it is already a daily task for me.
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In the spring of 2021, I was able to develop a digital alarm clock with two I2C devices without a soft CPU (only using FSMs)—one for the OLED display and one for the RTC clock. Of course, I did it all from scratch and without any simulation. After that project, I started my first
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Hey, hey. Who would have thought? The KianV RV32IMA SV32 Linux SoC runs with X11. What awesome stuff you can do with the
#FPGA
! :) music by
@therealh0ffman
#linux
#X11
#riscv
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I don't know who that is. But I can only say that he is light years ahead of all of us. Really intense knowledge concentrated. Just insane. Or he's the kind of guy who develops the latest chips for apple and fools us with his hobby projects.
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Another visitor. I found another video from my early days of logic design—a SR flip-flop built using transistors and diodes. Lovely.
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So, now I have equipped my IceStick HX1K, which has 1280 LUTs, with my mini KianV processor + audio device. This was much easier than on my Unix SoC :).
#FPGA
IceStick music machine.
@BrunoLevy01
, we will also integrate this into your processor :)
#verilog
4life
#yosys
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my daughter sent me a TikTok video with the same setup and asked me if I can do it too. I told her, of course, it's child's play.
#riscv
#esp32
#micropython
#engineering
#rocketscienes
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A major problem with logic design is that once you start with it, you don't want to use ready-made MCUs or application processors from manufacturers for your projects anymore. It just feels boring. (pic from )
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xv6 is amazing, my new hobby is studying everything about xv6. Awesome! The best! Now I have changed the linker script and pages, so that we really keep kernel text, read-only data, data, and bss in separate pages with the corresponding attributes. Writing access to read-only
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Nothing new, just avoiding an unhealthy desk. But a C program that makes a ball bounce on a VT220 terminal on the Kianv FPGA RISC-V Linux SoC—that's nice. And a nice Amiga tune—nice day, see you!
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If you'd like to give a chance kianV
#RiscV
bare metal and write C programs for it, that's great. The Verilog code is structured well, then anyone with "Computer Architecture" by Harris should be able to understand it and generate nice RTL from it.
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Xv6 requires a subset of PLIC. Now, the KianV RISC-V Linux SoC can run fully xv6 with 8 MiB SDRAM on the Colorlight i9 board from
@MIT
. I learned from Michael Schroeder’s xv6 ice40 RISC-V FPGA project and adjusted my SoC accordingly.
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Exciting news! The KianV RISC-V RV32IMA SV32 SoC, featuring the latest stable Linux kernel 6.9.10, has been released today. :)
@linuxfoundation
@Linus__Torvalds
@LF_Europe
@linuxdotcom
@obr2021
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Because I'm reading Design of the RISC-V Instruction Set Architecture, I quote the following:
"ARMv7 is vast and complicated. Between ARM and Thumb, there are over 600 instructions in the integer ISA alone. NEON, the integer SIMD and floating-point extension, adds hundreds more.
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I'm going crazy, my swapping works. I wrote a program that allocates 50 MiB of memory and then writes to it bit by bit. My SDRAM memory loses memory, and then parts of the process are swapped out to the SD card with a 10 MiB partition. It's crazy.
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If we're lucky, we might have the world's first ulinux RISC-V chip TT05.
#tinytapeout
#TinyTapeout
5 chips just received from
@efabless
! We've already tested the chip and confirmed our test designs work.
Next step is PCBA and then order fulfillment!
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I love that tweet. I implemented my first SDRAM controller using a logic analyzer, even before I developed a processor. I used a state machine that writes to, reads from, and tests the memory. I managed to achieve over 100MHz on the ICE40.
#ice40k
#blackicemk
I implemented a
#sdram
#controller
from scratch in
#verilog
behaves like a dual ported sram. Impossible without
#fpga4fun
and reading other implementations. Operates 64MHz with ram test. Shortcut produced an error and the statemachine will stop after an error
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Let's celebrate c code displays RISC-V logo that I cross-compile via my toolchain and then launch the ELF binary over my telnet session through NFS. KianV RISC-V Linux SoC
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I came 2021, I saw, and I implemented :)
I was obsessed, I was obsessed. Fortunately, I'm back to normal and thinking more about BMX and yoga. That's better for creativity and health.
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Don't fuck with Linux systems engineers. The KianV RISC-V SoC, running the latest mainline Linux kernel 6.12.0-rc1—now that's amazing ;)
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Another project. It's good to have a vacation. A terror velocity elastic simulation in C. God bless the laws of physics. VT220 simulation on the KianV RISC-V FPGA Linux SoC... changing the rules.
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I have the whole week off and have planned to spend the next few days playing around with Vivado. I do have the right computer now.
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It's crazy that released kernel 6.10.2 today, but it's no problem for me, the logic destroyer, to run the kernel on the KianV RV32IMA SV32 SoC. Cutting edge technology, hahahahahahah :)
@obr2021
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Don't fuck with Linux systems engineers and wannabe logic designer . The KianV RISC-V Linux SoC, running the latest stable Linux kernel 6.10.1, was published today :)
@obr2021
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While having lunch, I'm learning Python on a Kianv SoC using my smartphone.
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I bought a book by a deceased German computing pioneer who once developed one of the fastest supercomputers, the Suprenum computer.Perhaps I can adopt something from it that might be helpful for my KianV Stealth.
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