Matthew Venn
@matthewvenn
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Engineer and Technology Communication. On a mission to make ASICs more accessible. YosysHQ & Tiny Tapeout founder member. @matthewvenn @chaos .social
Valencia, Spain
Joined January 2009
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Still can't quite believe I have a clock on my desk that is powered by a chip I designed!
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This looks like a pretty simple computer program right? Maybe a while loop, a delay and writing some data to an output port?
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Are you interested in a 2 hour lecture/workshop titled "0 to ASIC in 2 hours" ? Thinking of applying to
@hackaday
#remoticon
. Feedback on my draft application appreciated!
#asic
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I was surprised to hear that moving data is 6400 times more energy hungry than doing an operation in a CPU!
That’s because the wires to move the data about are orders of magnitude longer than the wires in the ALU and are harder to wiggle up and down.
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I drew a CMOS inverter in magic and then simulated it in ngspice! Bring on the era of open silicon!
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Ever wanted to design your own microchip?
#TinyTapeout
6 is now open for submissions!
TT06 builds on TT05, with the same space, IOs and speed, but now adds power gating for all designs, mixed signal support and analog pins.
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#SiliWiz
is finally publicly available! Try it here:
And make sure you take a look at the lessons:
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.
@securelyfitz
that paper about dopant based hardware trojans is insane! Thanks for the recommendation!
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My first paper has just been published in the IEEE solid state circuits magazine!
Tiny Tapeout: A Shared Silicon Tapeout Platform Accessible To Everyone
If you're not a member, you can read the pre-print here:
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#OpenSourceASIChighlight
SOFA (Skywater Opensource FPGAs) are open-source FPGA IPs using the open-source Skywater 130nm PDK and OpenFPGA, an open-source FPGA IP generator for highly-customizable FPGA architectures.
#ASIC
#UofU
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Analog microelectronics is so interesting! Pretty much everything you make is also a temperature sensor!
To make a voltage reference that stays (mostly) temperature invariant, this bandgap circuit adds two elements with both positive and negative temperature dependence.
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World's first certified open source hardware down to the ASIC?
I plan to put a very limited number on
@tindie
and donate the proceeds to
@oshwassociation
. Thanks
@oshpark
for the boards!
Learn how to design your own chips on the !
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Riscure's
@jzvw
designed a chip and taped out on Sky130, then decapped it and sniffed the AES keys with a near field probe!
We talk about it in the next Efabless webinar:
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#OpenSourceASIChighlight
Super Hitachi (SH)-2 CPU with 2-Stage Pipeline on MPW8. Shumpei Kawasaki submitted this processor based on patents that expired in 2014.
This chip appears to have computational power w/a small footprint.
#ASIC
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We just closed
#Tinytapeout
2! Amazing turnout with 144 projects (and a few more I need to add from schools and universities).
Check the datasheet:
If you missed it, don't worry we'll be doing TT03 sometime in the new year.
Happy Friday!🎉
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EU Chips act:
... proposed to invest in a European open source EDA tooling ecosystem, encouraging open interchange formats and making sure current tools do not introduce restrictions on the utilization of open source hardware designs.
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I'm working on a new video about how flip flops work. Where does setup and hold come from? What is metastability? How do you build one out of CMOS? What other questions do you have?
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Finally submitted our
#ASIC
application to
@google
/
@SkyWaterFoundry
/
@efabless
! It was a huge amount of work and I'd like to thank the whole team for supporting me. I will be releasing course information in the next week - sign up if you're interested:
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Many thanks to
@mostlymoss
for these lovely 3D models of sky130 inverter and 4input nand. Very helpful in explaining my work, and lovely desk ornament!
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This Valentines day - what chip did you first fall in love with?
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I am going to put 500 small (100x100um) designs on an ASIC!
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Want to learn something new about the digital world we all take for granted?
#tinytapeout
teaches digital design basics and leads on to how chips are made.
Once you have a design, visualise it in your browser down to the lowest level of silicon!
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What you up to Matt?
Oh nothing, just designing ASICs on my way to demonstrate the open source tools at the Austrochip conference!
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I made my first FPGA board and it works! Thanks
@1bitsquared
and
@Olimex
for design inspiration. Thanks
@tnt
for the design review.
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Can I get a few more subs on my zero to asic YouTube channel? Once I get to 100 I can get a custom channel name! But a better reason is that I have my first interview on an analog design dropping this week. Stay tuned!
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It's been one year since I started getting interested in ASICs. Huge thanks to all the people who patiently helped me along the way. I wrote a post on my personal Zero to ASIC journey:
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Wednesday Open-Source ASIC Highlight!
5 GHz RF Transceiver design by
@thelithcore
Implements a dual-issue RV64 processor using SKY130B CMOS tech on MPW7.
The digital and top level were hardened using
@SiliconCompiler
with
@YosysHQ
and
@OpenRoad_EDA
.
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After 6 months, 90 participants and 14 projects submitted to MPW2, I have made some improvements to the Zero to ASIC Course. There's never been a better time to learn how to make your own chips!
Find out more here:
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FuseRISC is 2 RISCV processors with an eFPGA in between - supported by Yosys & NextPNR!
Check the interview with the FABulous FPGA team here:
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Today I am taping out another 5 chips, which takes me up to my 18th ASIC design!
2 chips are tests for the new
#GF180
PDK.
Then
#TinyTapeout
1 & 2, and a Zero to ASIC course submission. Between them they contain over 300 designs from hundreds of people around the world!
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Amazing documentation built right into the
#TinyTapeout
PCB!
Designed by
@PsychogenicTech
with
@kicad_pcb
.
I just donated to the Kicad fundraise - and you can too here:
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JT89 FPGA Clone of SN76489 hardware by Jose Tejada
@topapate
.
The SN76489 is a Texas Instruments chip from the 1980s used for sound generation on the BBC Micro, Sega Master System and lots more.
About 170 x 170 um on Sky130.
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Inspired by Satnam's cool Lego CMOS tweet, let's build and simulate the simplest functional part of his NOR gate - a MOSFET.
Follow along with the
#SiliWiz
tool:
🧵
I was playing with LEGOs with my daughter but then she worked out what I was doing and she was not impressed. An attempt at a (very poor) CMOS NOR-gate. The vertical red lines are polysilicon that provide the A and B inputs to the circuit. When polysilicon crosses n-type
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PCBs arrived from
@oshpark
for the ASIC clock! 0.072mm traces between BGA balls violate their design rules but I just did a connectivity test and everything buzzes out.
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Open source chip design
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Check out this cool 12 bit SAR ADC by Ricardo Nunes submitted to
#TinyTapeout
7!
Explore it yourself:
Project link:
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It's been a long time coming, but I finally have the world’s first certified open source ASIC hardware project as a kit you can buy!
For every kit sold, I will donate $100 to
@oshwassociation
More info:
Still can't quite believe I have a clock on my desk that is powered by a chip I designed!
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#sky130_mpw1
arrived! Thanks to everyone who made this happen!
Next steps will be to mount some bumped dies on the test boards and try
@tnt4all
's method of bringup.
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Great fun to do the 0 to ASIC presentation
@hackaday
#remoticon
! Slides here: . If you're interested in going deeper I am planning a paid course:
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Yes! I've finally 'reverse engineered' a standard cell more complicated than an inverter! This is a mux2 from
I knew staring long enough would work! Interested in a video?
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Did you know we had a secret analog design on
#TinyTapeout
5?
The design is a simple ring oscillator & DAC by Harald Pretl & Jakob Ratschenberger. Even more fun - they used an automatic layout tool called RALF!
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Check out this excellent upgrade to
#tinytapeout
build system by
@proppy
&
@maxiborga
- An interactive 3D viewer of the GDS!
Even does cell highlighting and layer control.
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#TinyTapeout
3 is open!
Learn how semiconductors work and design your own chip with our easy to use online tools.
Then we'll take 250 designs and manufacture them into a real chip with
@efabless
!
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#OpenSourceASIChighlight
HEHECore by the RIOS Lab () is a 64-bit, dual-issue, out-of-order RISC-V processor designed in Verilog. The creators seek to lower the threshold for CPU design using
#opensource
tools. Great work!
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Goodbye
@hackaday
Berlin! Lovely conference as always and great to see old friends and make some new ones!
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FPGA is the
#ASIC
terminology of the week!
In the last month, FPGA has been the 33rd most popular out of 42 terms.
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31b-PrimeDetector is the
#TinyTapeout
design of the week!
It takes in a 31-bit number and attempts to divide the value by all numbers less than it; if it finds one that divides evenly, the logic stops and declares the number not prime.
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First chip designed with ChatGPT? An interview with Dr. Hammond Pearce & Jason Blocklove.
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Had an amazing trip to IHP foundry and got some amazing semiconductor footage! Looking forward to sharing it with you all soon!
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Tomorrow I'll be talking about getting started with open source silicon. Join and ask me questions!
Register here:
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This part covered by the !
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My 4th analog layout in 4 weeks is this transmission gate. It's for
#TinyTapeout
6 analog mux.
I'm using all this experience to help me make a new
#analog
microelectronics course.
Sign up to my mailing list to get notified when it's available!
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Just started my trip to the Swiss Light Source!
Very excited to xray my first
#ASIC
chips and compare it to the design I sent to
@efabless
and
@SkyWaterFoundry
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#TinyTapeout
5 is open! Closing date is 4th of November.
26 IOs, ~50MHz IO,
$100 for 100x160um (pay extra for more space) and 1 chip delivered with PCB
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#tinytapeout
motherboard lives! The chip is one of my ASICs from last year, useful for testing the board.
Thanks
@AislerHQ
for sponsoring the boards,
@efabless
for the chips and
@PsychogenicTech
for the board design.
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Pretty satisfying to actually take the time to draw schematics by hand. Could probably do a nice job in kicad too. Preference?
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Interested to level up your digital design with
@tnt
and
@whitequark
?
I'm gauging interest with this form:
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Last few days to try the demo before I submit to
@Efabless
MPW7!
Keep reading to hear some feedback from some early adopters...
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Introducing SiliWiz!
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I just discovered Pyro, a Python lib that lets me expose a class on a remote machine and use it locally. Awesome for test harnesses. Here the remote is communicating with an FPGA design over SPI. On the local machine I control a power supply and then make remote measurements.
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This ASIC hat has a 5x drive strength for driving nets with a high fanout.
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Look at this cool interdigitated transistor! This is a way of building chonkier transistors by putting them in parallel. This one has 3 gates, 2 sources and 2 drains and can work at 5v.
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really great video from
@BreakingTaps
about how MEMS accelerators and gyros work - go watch!
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Worked hard to dump my brain's ASIC terminology contents before I forget it: 7k words in 2 days! Let me know if you think something is missing.
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Had fun presenting open source EDA to MaxLinear here in Valencia.
Presentation:
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Find out how MOSFETs are made at IHP
@waferffo
!
This video takes you on the journey of building a single MOSFET, up to the first metal layers.
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I'm interviewing Lakshmi tomorrow about their PLL design for the
@google
/
@efabless
/
@SkyWaterFoundry
#ASIC
shuttle.
What questions would you like to ask?
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Did you know it's possible to do
#ASIC
mixed signal circuit designs using only digital standard cells? Check out this
#interview
with Harald Pretl about his
#TinyTapeout
3 design:
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Met lots of great people and saw lots of great projects at Austrochip...
Check out this cool 3d printed model of a CMOS inverter by Ehrentraud!
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Today at
@hackaday
supercon we ran a 3 hour
#tinytapeout
workshop for 30 people and almost everyone got a simple design submitted to tt05!
Last 12 hours to get your designs in!
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I made a sweet illuminated desk stand for a photolithography mask!
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If you're interested in the ETH Zurich summer school on open source chip design (and more), follow my posts over on linkedin.
#EFCLsummer
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Had a play with printing the GDS files for my first ASIC.
#digitaltweed
. I think my choice of layers and colours for the whole chip works quite well...
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Join us for the launch of
#TinyTapeout
4!
* Exciting new features of TT04
* Discount codes giveaway
* Special guest and collaborator Uri Shaked
* Coolest designs of TT03
* Demo - how to create and submit an ASIC design
* Q&A
Register:
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