tenderizzation
@tenderizzation
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~~talk to me about your most recent illegal memory access~~ classically trained shitposter; running stock angle no turbo; pytorch CI breaker
South Silly Valley (南湾）
Joined July 2010
DM me "hey" I'll debug your CUDA error: an illegal memory access🍒 "hi" I'll debug your cuDNN error: CUDNN_STATUS_BAD_PARAM 🍑 "howdy" I'll debug your CUDA error: CUBLAS_STATUS_EXECUTION_FAILED 🍓
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@stochasticchasm i think the latent reasoning pill take is that every entry in your KV-cache is pigeonholed into producing something legible at the output though with R1-style CoTs this can go away with enough RL a model can just dual-purpose some tokens to be “output/legible” vs. “CoT”
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(this will now be a thread for my foremost passion in life: beverages)
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“crafting the ISA” is really doing a lot of heavy lifting here as i mean designing an ISA with knowledge of what is cheap and expensive to implement in hardware in terms of power and area etc in (combination with/opposition to?) software flexibility
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@_xjdr excited to see whether Grace (code compilation) or Blackwell (code generation/eval) in a GB system is the bottleneck in this setup
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every time i’m on a long haul flight on a boeing of a certain era i have a staredown with the “lavatory occupied” sign—not because i’m waiting but because of how painfully and hypnotically helvetica it is
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you need 8xh200 to fit R1 in memory he’s a phony get him
I'll have you know, Potter, my father rented out an 8xh100 for me so I could play around with R1 fine tunes. And not the cheap crappy distills that the weasleys have
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@_imdawon bro must be loaded willing to risk getting road salt on a corolla for some maccas 😭😭😭
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