🌿 lithos
@lithos_graphein
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Semiconductors - Follow me to learn all about microchips & how we print them. My web scraper is a live dashboard for the freshest tech news & press releases.
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🌿Fresh.
ChinaTalk: ASML's scanner service & parts export licenses.
@jordanschnyc
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🇰🇷 Korean researchers fabricated a transistor with a gate length of 4 angstroms.
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@Timcast
Anyone who watched the live streams that day knew this all along. The police were taking selfies with the protestors.
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@wikileaks
@theintercept
He wanted to be neutral and that wasn't allowed.
“We are friends of Russia, and we are also friends of the United States. We are friends of China and Europe. We are not part of any alliance.”
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ASML's EUV mirrors made by Zeiss have a surface that is so flat the imperfections are measured on the picometer scale, or a trillionth of a meter. This is equivalent to keeping an area the size of California as flat as a human hair.
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Everyone associates ASML, a relatively obscure Dutch company, with EUV Lithography, but here's a good list of the other companies also supporting this emerging market that made the AI era possible.
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Not sure they thought this one through.
"ASML risks losing access to the Chinese market ‘permanently’ if it implements the latest US export curbs."
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EUV scanners gobble up hydrogen.
With the first high-NA EUV system shipped, we are starting to see more pictures of what an assembled system looks like. No, I'm not talking about a big white box we were used to seeing inside fabs or CAD cartoon drawings, but real pictures of the
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“The chips team didn’t exist, now I have 200 people working for me on chips.” // “Commerce Department budget was $9 billion, now it’s $150 billion.”
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It took just over 3 decades and a global effort to commercialize EUV lithography.
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They've created a monster.
- 4 trillion transistors
- 900,000 AI cores
- 125 petaflops of peak AI performance
- 44GB on-chip SRAM
- 5nm TSMC process
- External memory: 1.5TB, 12TB, or 1.2PB
- Trains AI models up to 24 trillion parameters
- Cluster size of up to 2048 CS-3 systems
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TechWar: China's Lithography Problem.
China's Shanghai Micro Electronics Equipment Group Co., Ltd. (SMEE) won't be able to make a sanctions-busting immersion scanner in the next decade, and I will explain exactly why. This is not a putdown on China's technological capabilities;
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Tesla's full wafer super computer chip. Harvested by TSMC in Arrakis.
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This is not a sci-fi movie. Scenes from ZEISS Semiconductor Optics in Germany—making the key lens components for today's digital Spice Harvesters.
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@rawsalerts
It's a good resume builder for Senate Foreign Relations Committee Chair. International experience.
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TSMC's Complimentary Field Effect Transistors (CFETs)—some of the geometries in this image are on the single-digit nanometer scale. You could fit about 150 of these cubes inside a red blood cell and each one contains 24 transistors. That's a total of 3600, litho frens can check
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@JackPosobiec
Kindergarteners take the train to school on their own there. It's the safest place on Earth.
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LAM just dropped a whitepaper on scaling Flash Memory to 1000+ layers using Cryogenic Dry Etch processing. That's an impressive SEM image at the right. Flawless.
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State of the Art Lithography.
Fresh High-NA EUV results from imec/ASML. These are 9.5 nanometer lines here, after pattern xfer into (presumably) a hardmask like SiN or SOG. It's tone inverted for metal, so I'd guess a negative Metal Oxide Photoresist was used. This was done with
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First on-chip laser array: Photonics chips have limited scalability bc they currently need an external light source. This is a way around that barrier. These nanoscale lasers are only 400nm wide. Impressive SEM image! 😍
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Rumor has it ASML will stop servicing Chinese immersion scanners below (in red) starting next year. Some of them are >10 years old already. That's a huge number of tools and it can't be allowed to happen given the dollar value we are talking about here. ASML will have to offer a
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AI-era Marvels:
ASML's mag-lev stages can accelerate up to 15G. For comparison, modern fighter jets operate no greater than 10G. These tools are used to pattern chip components on the nanometer scale. At these speeds, the stages are still capable of maintaining a positional
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40 years ago 🇺🇸GCA, 🇯🇵Nikon and 🇺🇸Ultratech dominated the advanced lithography tool market.
🇳🇱ASML didn't even exist. Now they own it all.
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What does it mean to "tape out" a microchip?
Tape out refers to making the master circuit patterns that are used to mass-produce semiconductor devices. This lingo originally referred to the large spools of tape (at left) that stored all the data that would write the image of the
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Nanoimprint finds a real semiconductor application.
Micron shared a talk yesterday on how NIL could be used for certain DRAM layers. They set this up by showing a trend where what's called "chop" layers are increasing for DRAM nodes and going below the resolution for immersion
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imec demonstrates Copper Hybrid Wafer Bonding down to 400nm pitch interconnect. That'd be about 6.2 million connections per square millimeter. Impressive! It looks like the placement error is on the order of +/- 50nm.
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🌎 Litho World Record.
Researchers in Switzerland used an EUV test system to pattern down to the 6 nanometer half pitch. They used an optical trick called interference lithography, so it's not commercially viable. This method has been used to test the resolution of photoresist
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Nvidia designs chip. TSMC makes chip. TSMC sells chip. TSMC buys chip back to make more chips. What a great business model.
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Intel posted the high-NA EUV tool install video they shared at SPIE last week. This is the last frame showing what's been installed (in green).
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🌿 Fresh.
Tokyo Electron just launched their version of the EUV pattern shaping system (Acrevia) to compete with Applied Material's (Sculpta) tool.
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@DC_Draino
I remember when a toilet overflowing in Georgia didnt affect the entire state of Alaska.
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This is a new image of the Velhoven High-NA EUV tool assembly that I just saw today. It was in a Tom's Hardware article crediting ASML. It shows the ASML team performing the last part of the installation, which is dropping the upper part of the tool with the cleanroom crane. The
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This is an electrical switch that is a single molecule just 1 nanometer in size. Fabricated by the Max-Planck Society in Berlin.
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SK Hynix will begin shipping 400 layer NAND Flash Memory next year using hybrid wafer bonding. The described method patterns the memory cell and peripheral circuitry on different wafers, then bonds them together in the packaging process.
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How ASML became
#1
: Printing Economics.
The lens system inside a scanner is the single most expensive tool component in a semiconductor fab. Back in the early 2000s, ASML released their TwinScan platform to address the growing need to maximize a fab's investment in scanner
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xMEMS just released the first fan-on-chip micromachine for cooling mobile device chips. It is just 1 mm thick, makes no sounds, and can be top- or side-ventilated.
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🇯🇵 Lasertec's new high-NA EUV mask inspection tool will also use a larger anamorphic lens to match 🇳🇱 ASML's scanner.
Source: August 12th, 🇰🇷 Samsung Electronics, Dr. Min Cheol-gi's presentation slides at the 2024 Next Generation Lithography + Patterning Conference in Suwon,
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Intel published 450Mb of detailed plans for their Magdeburg, Germany, site online. Fab 29.1 and Fab 29.2 will be high-NA EUV capable fabs with an operational start in Q4 2027.
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🍎 Fresh.
@intheMatrixxx
@The_AuthorityQ
@GusQuixote
@ElizabethPDove
@cpage86_
Well well well. Look what came across my feed. The FBI just declassified their investigation into Q.
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I like how we're now adding the EUV tool into these charts but what's needed is the patterning flow that goes with it. SADP + Cut, LELE, etc.
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