#PCIExpress
5.0,
#PCISIG
’s newest specification, is now available to members.
#PCIe
5.0 doubles the bandwidth of PCIe 4.0 and increases performance in a variety of high performance markets. Read the press release to discover the features of PCIe 5.0:
The release of the
#PCIe
6.0 specification, version 0.9 to members brings us one step closer to final release of the specification later this year. No additional functional changes are expected during this member review period. Read more in the blog >
The
#PCIe
6.0 specification is here. Interested in learning more? Explore PCIe 6.0 specification resources, educational materials and more on the
#PCISIG
website >
#PCISIG
is proud to announce the upcoming
#PCIExpress
6.0 specification targeted for release in 2021.
#PCIe
6.0 will reach 64GT/s, utilize PAM-4 and pave the way for future innovation. Read the press release to discover the features:
#PCISIGDevCon19
Attention press and analysts: The
#PCISIG
virtual Press Conference will be on June 3 at 10:00 am PT. PCI-SIG leadership Al Yanes and Richard Solomon will share the latest updates on
#PCIe
6.0 specification and more. DM PCI-SIG to receive details on how you can attend.
"PCIe... is the catalyst for the development of many other technologies, such as storage, networking, GPUs, chipsets, and many other devices" -
@PaulyAlcorn
,
@tomshardware
. Read the full article and learn about new
#PCIe
4.0 and 5.0 features:
The
#PCIe
6.0 specification is on track for release in 2021. The next generation of PCIe technology will deliver blazing 64 GT/s per lane bandwidth. Read the
@HotHardware
article by
@Paul_B_Lilly
for details >
#PCIExpress
6.0, will stay ahead of the I/O bandwidth curve by delivering 256GB/s via x16 configuration. Discover how the
#PCIe
6.0 spec will accomplish these performance jumps:
@jonfingas
@engadget
Want to learn more about the
#PCIe
7.0 specification? View the
#PCISIG
FAQ to dive into the PCIe 7.0 feature goals, expected data rate and anticipated markets >
Attending
#FMS2022
in Santa Clara, CA this week?
#PCISIG
President and Board Chair Al Yanes will present “
#PCIe
6.0 Specification: An Interconnect for the Next Generation of Storage” on Aug. 3 at 9:45 am PT. Add the session to your conference agenda >
The latest blog by
#PCISIG
Protocol Work Group Chair David Harriman of
@AmpereComputing
“
#PCIe
6.0 Specification Functionality Updates – Part 2” explores new link functionality, the introduction of
#L0p
and more. Read the blog >
#PCIe
6.0 technology with Flits (fixed-size flow control units) for lightweight FEC and
#PAM4
signaling means that the ecosystem can start building and validating designs to the new standard. Read the
@ServeTheHome
article for details >
#ICYMI
: The latest blog by
#PCISIG
Protocol Work Group Chair David Harriman of
@AmpereComputing
“
#PCIe
6.0 Specification Functionality Updates – Part 2” explores the addition of segment numbers to TLP headers and more. Read the blog >
Celebrating 30 years of
#PCISIG
innovation with the introduction of
#PCIe
7.0 specification, targeted for 2025. The next generation of PCIe technology will double the bandwidth to 128 GT/s, utilizing
#PAM4
signaling and Flit-based encoding. Read the blog >
With the release of the
#PCIe
6.0 specification,
#PCISIG
once again doubles the I/O bandwidth to 64 GT/s, enabling next-generation applications like
#AI
and
#ML
. Dive into the article by PCI-SIG Board member Debendra Das Sharma of
@intel
to learn more >
The next generation of the ubiquitous bus is once again doubling the data rate of a
#PCIe
lane to 8GB/second in each direction – and far higher for multi-lane configurations. Check out the
@anandtech
article by
@RyanSmithAT
for more >
#PCISIG
is excited to share
@SD_Association
’s latest innovation: MicroSD cards that use the
#PCIe
3.0 interface to deliver up to 985 MB/s transfer rate. Read the full release:
The
#PCIExpress
6.0 specification's 64 GT/s transfer rate will support major advancements for servers and foster innovation among a new generation of products leveraging the
#PCIe
6.0 spec. Look back at the evolution of previous specifications:
@Techgage
Attend the
#PCISIG
#SDC2023
presentation “
#PCIe
7.0 Specification: 128 GT/s Bandwidth for Future Data-Intensive Markets” on September 20 at 10:35 am PT, presented by Debendra Das Sharma. Learn more on the event agenda:
The upcoming
#PCIe
6.0 specification will enable technology in emerging markets such as
#AI
,
#MachineLearning
,
#HPC
and more. Read the article from
@HotHardware
to learn how the spec is built to support the next generation of data-demanding systems:
Version 0.5 of the
#PCIe
6.0 specification has been released and is on track to be finalized in 2021. The spec will deliver a 64GT/s data rate, PAM-4 encoding and will maintain backwards compatibility. Read more in the article from
@tomshardware
:
New
#PCIe
5.0 features include electrical changes to improve signal integrity, backward-compatible CEM connectors for add-in cards, and more. An article from
@tomshardware
@PaulyAlcorn
highlights everything you can expect from the 2019 release:
High bandwidth and low latency are two of the many reasons why
#PCIe
technology has evolved to become the primary I/O interconnect in the
#IoT
space. Read
@ElectronicDesgn
article by Debendra Das Sharma and Anil Kumar of
@intel
>
Behind the scenes of our video interview with
@GestaltIT
on-site at
#FMS23
. Stay tuned for the video feat.
#PCISIG
vice president Richard Solomon where he discusses the latest updates of the
#PCIe
specifications in the industry and the our new
#optical
workgroup
#TBT
: Our MOU agreement with
@ComputeExLink
(
#CXL
) establishes a liaison framework between the two organizations to ensure consistent joint messaging and marketing across areas of mutual interest. Read the blog for details >
#PCIe
6.0 specification, the next generation of the ubiquitous
#PCIe
bus is once again doubling the data rate of a PCIe lane, bringing it to 8 GB/s in each direction. Read the article by
@RyanSmithAT
in
@anandtech
for details >
Last week,
#PCISIG
announced the formation of a new workgroup to deliver
#PCIe
technology over
#optical
. Meet with PCI-SIG representatives at
#FMS2023
at booth
#725
to learn more about the announcement. View the full press release >
#PCIe
7.0 specification represents an effective 8x increase in bandwidth compared to what’s actually available today. The first PCIe 5.0 devices should be available towards the end of this year, writes
@ExtremeTech
Read the article >
The PCIe 6.0 specification integrates industry-leading features, like
#PAM4
signaling and Flit-based encoding, to deliver a 64 GT/s data rate. Watch the video to learn how the PCIe 6.0 specification will meet the needs of data-centric applications >
Where will
#PCISIG
go next? Manmeet Walia will be presenting an update on the organization and
#PCIe
technology at
@embedded_world
in the
@SD_Association
booth (3A-524). Learn more about our upcoming industry events:
“PCIe 5.0 allows up to 128 GB/s bandwidth, twice that of PCIe 4.0. The PCIe 5.0 architecture also implements electrical changes to improve signal integrity and mechanical performance of connectors”-
@tomshardware
. Learn the highlights of the
#PCIe
5.0 spec:
#PCISIG
recently announced our technical workgroups are beginning development on the
#PCIe
7.0 specification. Targeted for release in 2025, PCIe 7.0 specification is planned to deliver 128 GT/s data rate. Read the blog for details >
#PCISIG
member Dean Gonzales of
@AMD
is one of the recipients of the
#PCISIGDevCon23
Chairperson’s Award. Read this interview to learn more about how he has contributed to the electrical
#PCIe
specification >
Marketing Work Group Co-Chairs Mihaela Erler (
@intel
) and Scott Knowlton (
@synopsys
) explain the benefits of becoming a
#PCISIG
member, including participation in
#PCIe
Compliance Workshops and contributing to technical work groups. Watch the video >
#PCISIG
recently announced a marketing MOU agreement with
@ComputeExLink
to increase awareness of industry standard interconnect technologies and provide collaborative educational messaging. Read the blog >
Want to learn more about the
#PCIe
7.0 specification? Listen to the latest
@StorageUnpacked
podcast with
#PCISIG
President Al Yanes for a deep dive on upcoming improvements >
#PCISIG
President and Board Chair Al Yanes recently sat down with
@storagereview
podcast host
@BMBeeler
to discuss the design aspects, profiles and system changes needed to take advantage of the
#PCIe
6.0 specification. Listen to the podcast >
Join us on Wednesday, Jan. 25 at 8:00 am PT for the upcoming
#PCISIG
webinar hosted by
@TeledyneLecroy
. The talk will provide an overview of
#PCIe
5.0 protocol and electrical compliance testing. Register here>
“MicroSD cards are about to get a whole lot faster, thanks to the newly announced microSD Express format that the SD Association announced at MWC 2019”-
@cgartenberg
,
@verge
. Discover how
#PCIe
technology has made this possible:
@SD_Association
Each new generation of
#PCIe
technology meets the needs of various systems. The PCIe 6.0 spec will provide support for bandwidth-intensive systems such as
#HPC
clusters or large
#supercomputers
. Discover the potential of this spec:
@TweakTown
@punx223
Key benefits of
#PCIe
6.0 technology include double the bandwidth, low latency and backwards compatibility. View the infographic to learn the new features of the PCIe 6.0 specification and its impact on the industry >
We are pleased to announce that the
#PCIe
7.0 specification version 0.5 is now available for member review. With this release, the PCIe 7.0 specification remains on track for full release in 2025. Learn more >
The advantages of
#PCIe
technology for automotive short reach include native PCIe support by CPUs, SOCs (system on chips) and FPGAs (field programmable gate arrays). Attend the live webinar to explore the benefits >
#PCISIG
’s new specification,
#PCIExpress
5.0, opens up a world of possibilities for new age applications.
#PCIe
5.0 doubles the bandwidth of PCIe 4.0 and maintains backwards compatibility. Become a member and help shape future specs:
“With the forthcoming
#PCIe
7.0 specification,
#PCISIG
continues our 30-year commitment to delivering industry-leading specifications that push the boundaries of innovation.”
– PCI-SIG President Al Yanes
View the press release >
With the
#PCIe
6.0 specification, version 0.9 release,
#PCISIG
has plans to bring the performance of its interconnection standard to new heights with double the data rate over the PCIe 5.0 specification. Read the article
@OC3D
article by
@WYP_PC
>
The goal is to double the available bandwidth of its predecessor, which in
#PCIe
7.0 specification’s case means that a single PCIe 7.0 lane will be able to transmit at speeds of up to 32GB per second, writes
@AndrewWrites
Read the
@arstechnica
article >
The latest “Meet the
#PCISIG
Members” blog features
@AsteraLabs
as they discuss their participation in developing
#PCIe
technology and the advantages of PCI-SIG membership. Read the blog >
A special thanks to
#PCISIG
members who participated in Compliance Workshop
#121
this past week in Seoul, South Korea. Visit our website to learn more about upcoming events and Compliance Workshops >
#PCISIGDevCon22
kicks off tomorrow (6/21) in Santa Clara, CA. Unable to attend the event in person? Free virtual attendance is also available for PCI-SIG members. View the conference agenda on our website >
#ICYMI
:
#PCI
-SIG Board Member Debendra Das Sharma from
@Intel
provides an overview of
#PCIe
6.0 specifications features. Learn more about the PCIe 6.0 specification in this video on our YouTube >
#PCISIG
Vice President Richard Solomon was recognized for his years of PCI-SIG service with the DevCon 2022 Chairperson’s Award. He discusses his work advancing
#PCIe
technology in the blog >
Are you attending
#FMS22
? Visit the PCI-SIG pod in the
@SD_Association
booth to learn more about how SD Cards and
#PCIe
technology work together. We look forward to seeing you at booth 833 until 7:00 pm tonight.
#ICYMI
: Check out the latest
#PCISIG
webinar hosted by
@TeledyneLecroy
. The talk provided an overview of
#PCIe
5.0 protocol and electrical compliance testing. Watch the full webinar on YouTube >
With
#PCIe
5.0 technology SSD units expected to reach speeds of 13,000 MB/s, the first
#PCIe
6.0 technology
#SSDs
could perform at speeds of up to 25,000 MB/s, according to
@Gadget_Tendency
See the article for details >
#PCIe
architecture is a natural fit for the automotive market, given its scalability, performance and durability. Watch the video from
@MicrochipTech
for a look at PCIe technology growth in
#automotive
>
#PCISIG
has reached a milestone on the
#PCIe
spec roadmap: Version 0.5 of the PCIe 6.0 spec was released to members. The spec will offer a 64GT/s data rate for emerging applications such as
#AI
and machine learning. Learn more:
@tomshardware
@NBroekhuijsen
The recent
#PCISIG
webinar hosted by
@TeledyneLecroy
explores Protocol and Electrical Compliance Testing for
#PCIe
5.0 systems. Watch the webinar on YouTube >
The
#PCIe
6.0 spec "will help fuel future generations of interconnected devices, while allowing today's storage speeds to be accessed with fewer resources” -
@WYP_PC
. Learn how the PCIe 6.0 spec, now in Version 0.5, will support various technologies:
@OC3D
#PCISIG
Marketing Work Group Co-Chair Scott Knowlton of
@synopsys
is one of the recipients of the
#PCISIGDevCon23
Chairperson’s Award. Read this interview to learn more about how he works to advance industry knowledge of the
#PCIe
specification >
The
#PCIe
6.0 spec's 64 GT/s transfer rate will pave the way for increased performance in new tech innovations, while maintaining backwards compatibility with previous specs. Discover the features of PCIe specs:
@appleinsider
@MalcolmOwen
#PCISIG
is excited to exhibit at
#IntelON
, taking place virtually today and tomorrow. Register for the free event and be sure to visit the PCI-SIG virtual booth in the Industry Enabling Zone to learn more about PCI-SIG and the
#PCIe
specifications >
@intel
The
#PCISIGDevCon24
returns to Taipei, Taiwan today and tomorrow. The event will include presentations from
#PCISIG
members discussing their implementations of
#PCIe
technology. See the agenda >
“
#PCIe
6.0 Specification: The Interconnect for I/O Needs of the Future” webinar begins in 10 minutes. Register now to attend the live webinar and participate in the Q&A after the presentation:
The
#PCIe
6.0 specification reached a milestone with v0.7 and is on track for finalization later this year. It will increase the data rate to 64GT/s via PAM-4 encoding. Learn more from
@tomshardware
>
The
#PCIe
6.0 specification can deliver record performance with new feature enhancements like
#PAM4
signaling and Forward Error Correction (FEC). Check out the FAQ to learn more about the technical details of the specification >
Next week,
#PCISIG
Board member Debendra Das Sharma of
@Intel
is joining the “Innovation with Load-Store Interconnects (
#PCIe
,
#CXL
,
#UCIe
) in Supercomputing Landscape”
@ISChpc
panel on May 24 at 1pm CET. View the full schedule >
#PCISIG
is pleased to share the
#PCIe
7.0 specification, version 0.3 is now available to members. Learn more about the latest version and how this milestone aligns with our full specification release schedule in our blog >