SemiAnalysis
@SemiAnalysis_
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Datacenter vs semiconductor fab: a typical hyperscale datacenter, such as Meta’s “H” building, has a power capacity of 50-100MW. This is akin to a small to mid-sized fab; however, we estimate TSMC’s “Gigafabs” require north of 200MW!
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Bigger isn’t always better? Rapidus, Japan’s gamble to start a brand new 2nm domestic foundry in 2027 has had many puzzled, but recently they revealed how.
They are touting the advantages of small batch processing as helping yield, cycle time, and more. Counter-intuitively, they
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1/4 - Chevron deference has just been struck down by the US Supreme Court. What is it and how does it affect semiconductor companies? ⬇️
Under that 40-yr-old legal doctrine, US federal agencies had the power to create their own rules & regulations when a law is ambiguous. In our
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"Bunny suits" are what people wear in semiconductor cleanrooms (>10,000x cleaner than a hospital operating room). The term was coined in Intel Fab 3, California in 1973: back then, “People used to find excuses to visit Fab 3 just so they could put a bunny suit on” !
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In the smartphone RF Front-end (RFFE) industry, a Chinese ecosystem is quickly emerging after years of stalling. The leader Maxscend, founded in 2006, saw its revenue surge 36x since 2017 and now has ~7% of the Android RFFE market, mostly with Chinese OEMs, but also Samsung.
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1/6 - We attended COOLChips 27, a conference focussed on lower power, high performance SoCs. This was held at the Takeda Building at Tokyo University. This building is named after its donor Ikuo Takeda, who founded what is today known as Advantest in 1954!
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EDA company Silvaco, $SILV, is pricing its IPO this Wednesday. Here’s our quick analysis. A thread ⬇️
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TSMC indeed has an energy footprint roughly equal to Google's and growing 10% CAGR 2016-22... but slower than hyperscalers (Google +17% CAGR)
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4/4 - In the most chaotic scenario – attempts at implementing controls could be made ineffective as new rules become snarled in time consuming legal battles, unable to keep pace with rapid technological developments in the Semiconductor industry.
However, Congress, if it
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Is GlobalFoundries lying again? "Dozens of GlobalFoundries employees were supposed to be on site by now. There is currently no one from this company here."
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The companies that stand the most to benefit from this are ASM International and Lam Research as they offer more comprehensive suits of single wafer ALD and single wafer etch product. Interestingly, Kokusai Electric, one of Japan’s largest equipment companies stands to lose out,
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3/4 - Now that Chevron has been struck down, it’s open season for Semiconductor product and equipment manufacturers to mount challenges to export regulations in the court system – as long as they can point to some ambiguity in the laws authorizing these export controls. With
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2/4 - The US Commerce Department’s Commerce Control List is a set of items subject to export controls and includes a plethora of Semiconductor products and manufacturing equipment. Currently over 500 pages long, items on the list are identified in exacting detail by Commerce
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WFE suppliers will love this since it means more tools needed. The downsides for chipmakers are higher cost and that metrology is much more difficult – wafers processed individually will all have unique signatures… we’ll see if Rapidus is right within a few years as they aim to
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3/6 - While presenters were mostly from academia, Intel presented their advanced packaging roadmap. IFS believes EMIB is better than CoWoS in every way with better cost, yield and cycle time and can match even CoWoS-L on performance (we are skeptical).
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Traditional flows use batch processing to increase speed and reduce cost, typically in chemical processes such as oxidation furnaces, CVD chambers, etc. Entire 25-wafer lots or more can be run at once, and a single high-capacity tool is cheaper than many smaller ones. 2/5
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And Hyperscaler energy consumption is set to accelerate even further, as we explained here:
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Rapidus claims that large isn’t always faster: the process is only as fast as the slowest wafer in a batch. And large chambers, for example in deposition tools, can take a while to heat or cool between batches. These benefits are even stronger in R&D, where rapid iteration is
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5/6 - Another interesting thing is this is the first time we have seen Intel publicly reveal package size limits for their various technologies. EMIB can go up to 6x reticle, and they want to achieve >8x reticle by 2028. Foveros today can go up to 4x reticle.
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2/6 - A key theme was AI consuming a lot of power and there was a lot of discussion on various ways to increase energy efficiency. You can read more about in our datacenter power piece.
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A LNA is typically built on RF CMOS or SiGe. A power amplifier (PA) amplifies a weak high-frequency RF signal generated by the transmitter within the handset to meet the power requirement of the communication base station. Main materials are SiGe and GaAs
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4/6 - Intel believes TSMC was first to market with CoWoS and that’s why it is so dominant. IFS is working to get customers to redesign and requalify their packages for EMIB. See our Accelerator Model for more on IFS packaging wins.
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We were at Embedded World last week to see how edge AI is progressing. Revolution alert, AI is coming to your washing machine!!! Jokes aside, there is some interesting progress, but the Memory Wall is strong and real AI is happening in datacenters...
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6/6 - Intel’s proprietary wafer sort capabilities can offer single die sort as well as standard wafer sort. Single die benefit: faster to change temperature vs entire wafer. This is needed as wafer probing is completed at various different temperatures
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After bragging about their large 7.5B€ project in France with STMicro, today a french media outlet reveals that GF's implication on that project is zero...
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A LNA amplifies the incoming signal from the antenna, making it large enough to be manipulated by the receiver without adding excessive noise, to achieve better signal, call quality and higher data transmission rate on mobile devices.
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A RF switch connects multiple RF signals and allows switching between reception/transmission, frequency bands, reducing interference and allowing smartphones to share antennas (cost saving). RF-SOI is the main underlying technology, but there are alternatives: RF CMOS, GaAs, MEMS
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This STMicro microcontroller runs a model which can estimate the weight of clothes in that washing machine with great accuracy, after just a few turns. This allows to remove some sensors, slightly reduce BOM, improve reliability, and reduce complexity as there is less hardware
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@ReznoirA
Both lol. Latter is about how large batch furnaces take so long to achieve appropriate chamber conditions vs single wafer.
Shorter cycle time better yield learnings.
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11 - SILV is cheaper on sales multiples, so the upside investors are playing for is if they can get close to SNPS and CDNS levels of profitability. Of course, that’s a big if and CDNS and SNPS are also far superior in terms of quality.
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2 - The EDA market is dominated by Cadence, Synopsys and Siemens Mentor with ~75% of the market. The remainder of the market is taken up by a long tail of smaller vendors. Silvaco is one of these small players with 2023 revenue of only $54mn, less than 1% of Synopsys’s scale!
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6- The challenging part of this is a key input: the fab’s own data. This is highly sensitive, requires a lot of trust, and involves heavy customization = lower margins. SILV is sub-scale and barely made a profit in 2023, after 2021 & 2022 losses, despite high gross margins (80%+)
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4- The main growth driver of EDA spend is the rising complexity of leading edge chip designs. However, in Silvaco’s key markets of power and display, it is less clear that R&D intensity is rising as much, as evidenced by lower revs growth despite being much smaller!
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9 - So how does SILV’s valuation compare to SNPS and CDNS? SNPS and CDNS both have better growth outlooks, stronger industry positions, and are more profitable. However, SILV is launching at a more expensive valuation.
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5- SILV now targets the fab “digital twin” market, to help customers simulate and improve production processes/lower cost/increase yield. Micron is the initial customer and invested $5mn into SILV in April. But mkt is very competitive, incl. internal solutions by TSMC and Samsung
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An RFFE is meant to improve signal quality, converting low-power radio frequency to high-power signals for transmission to a base station. The module sits between antennas and transceivers and main components are switches, Low-Noise Amplifiers (LNA), Power Amplifier (PA) and...
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7 - Gross profit is spent primarily on G&A, followed by R&D. Since 2021, SILV’s R&D spend is actually down (!) with S&M and G&A expenses up. This is due to IPO costs and R&D had to get cut to finance this.
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RF filters. They isolates radio signals from the different spectrum bands that phones use to receive and transmit information, and thus removes or accepts signals that fall in certain areas of the radio spectrum. As band count increases with each gen, more filters are required.
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10 - SILV’s margins are still low relative to management’s target of 25% non-GAAP operating margin so it may be too harsh to judge SILV on earnings multiples presently.
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8 - R&D investment is key for an EDA business to stay competitive and grow. Both CDNS and SNPS continue to grow their R&D investment while also spending more than SILV does on a % of sales basis. This shows just how hard it is for the small EDA players to try to close the gap
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3 - SILV is focused on TCAD for the Power, Display, and Memory markets. TCAD tools simulate device behaviour to validate performance before manufacturing. This is from SILV’s Victory simulator that is modelling Source Current at different Drain Voltages of a power MOSFET.
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@Simeon_Cps
Yes we have all frontier datacenters in planning and construction outside of China.
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